1. Field of the Invention
The present invention relates to electronic circuits comprising field effect transistors (FET), and more specifically to composite transistors comprising a plurality of FET devices.
2. Description of Related Art
Field-effect transistors (FET) are today the fundamental building block for the majority of integrated electronic circuits. These circuits include, but are not restricted to, integrated circuits for fiber optic communications systems, such as amplifiers and high-speed analog and digital circuits. Various types of FETs are implemented in a number of semiconductor technologies including silicon (CMOS), Gallium Arsenide (GaAs) and Indium Phosphide (InP).
FETs are widely used as active loads and current sources in integrated circuits. These applications employ the saturation region of the nonlinear channel current-voltage relation in which FETs behave as voltage-controlled current sources. The current in the FET channel, between the drain and source nodes, is controlled by the voltage applied between the gate node and the source node. In the saturation region, the channel current is largely independent of the voltage applied across the channelxe2x80x94this results in high impedance presented to AC signals while allowing substantial DC current to pass. Applications include the insertion of DC bias current (a current source) as well as signal current-to-voltage conversion (an xe2x80x9cactive loadxe2x80x9d) in amplifier circuits.
Applications such as fiber optic communications require circuits that operate near the speed limits of transistor technology. Fast FET devices like high electron mobility transistors (HEMT and PHEMT) fabricated in GaAs and InP, as well as silicon CMOS devices with ever smaller geometries, are being used in integrated circuits to meet these demands on switching speed and bandwidth. Traditional FET active load and current source circuits using high performance semiconductors become inadequate as the frequency of operation approaches the limits of the device.
FIG. 1a shows a stacked FET active load configuration 110. Two FETs W1101 and W2102 are coupled in series and each gate and source wired together. This circuit exhibits poor high frequency response due to the interaction between the impedances at the FET gate 103 and FET drain 104. In a high-frequency FET implementation, it may also exhibit negative resistance.
FIG. 1b shows a self-bootstrapped active load configuration 110. Two FETs 111 and 112 have their channels coupled in series, and both the gate 113 of FET 111 and the gate 114 of FET 112 are coupled to the source node 115 of FET 112. This circuit is not well suited to high-perfornance FET technologies, in which there is a single threshold voltage that is not variable by the circuit designer. This forces one FET device to operate near cutoff and the other in the triode region, with the result that the device periphery must be roughly twice that of the present invention to obtain the same DC current.
FIG. 1c is a cascode current source 120. Two FETs 121 and 122 are coupled with their channels in series, with bias voltages and AC ground presented to the gate terminals of both. This circuit is potentially unstable at high frequencies, and its overall stability is highly sensitive to the impedance presented to a gate 123 of FET 121, e.g. a small unavoidable inductance may lead to significant negative conductance at the output of the current source. Additionally, this circuit cannot be used as an active load with HEMT devices due to the lack of a P-type device.
Accordingly, there is a need for reliable high-performance active loads and current sources at higher frequencies.
The present invention is a circuit comprising two series-coupled field effect transistor (FET) devices with a resistor network coupled in parallel forming a composite device (that can be substituted directly for a single FET device). In applications such as active loads or current sources, the composite device exhibits a greater breakdown voltage and superior high-frequency characteristics. The resistor network provides optimum direct current (DC) bias for depletion mode devices and superior high-frequency impedance control. Bandwidth and stability are both increased. Furthermore, this circuit is compatible with depletion mode FET processes having a single fixed threshold voltage. Advantageously, the composite FET active load and current source in the present invention operates in an unconditionally stable state at all frequencies.